![]() ![]() It’s quite late here already and time to go to bed now. Just some remarks I noticed while toying around with your design. If you really want to keep +3V3VADC on internal layers for some reason, then route it around those signal lines. I assume the 4C16M16SA is some memory chip with lots of relatively high sped traffick? You really do not want to cut the GND plane below all those signal wires. For this reason the product is called Orzo, which means barley in Italian. This track cuts both trough the GND plane and through PWR.CU. Load image into Gallery viewer, Orzo in wooden scoop. I’m a bit surprised by the routing of +3.3VADC. For the decoupling capacitor it does help to bet better performance. The connection between the pad and the IC itself is already much longer then the via. ![]() I’m not sure if this is important though. I’ve also gotten into a habit myself of giving each GND pin 2 via’s, one on each side of the pad. Reason is you get the GND closer to all footprints, which reduces EMI. I would swap the PWR.Cu and GND.Cu layer. (Maybe someone with more knowledge can chime in too) There are a few things I would change though. Your PCB looks quite good, but I have not looked too deep into it (I’m also not an expert on this). 99 Quality Viewers Refill Guaranteed Starts within 3h Secure Payment. I’ve moved some via’s around a bit, and all unconnected items disappeared, so they were because of via’s too close together and the clearance of one via overlapped with a via that should not have clearance. For this reason, if you can find a way to get free YouTube views for your. ![]()
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